“Testing and validating the AC performance of high-precision, fast analog-to-digital converters (ADCs) with resolutions higher than 16 bits requires a near-perfect sine wave generator that supports at least 0kHz to 20kHz audio bandwidth.

“

Testing and validating the AC performance of high-precision, fast analog-to-digital converters (ADCs) with resolutions higher than 16 bits requires a near-perfect sine wave generator that supports at least 0kHz to 20kHz audio bandwidth.

These evaluations and characterizations are typically performed using expensive laboratory instrumentation, such as the Audio Precision AP27xx or APx5xx series of audio analyzers. In most cases, modern high-speed SARs and wideband ADCs with 24-bit or higher resolution use single-supply and fully differential inputs, requiring accurate DC and AC performance from the signal source used for the DUT, while providing fully differential outputs ( 180° out of phase).

Again, the noise and distortion levels of this AC generator should be much better than the specifications of these ADCs, with a noise floor well below C140dBc and distortion levels well below C120dBc according to most supplier specifications, with input signal audio frequency 1kHz or 2kHz, up to 20kHz. Refer to Figure 1 for a typical test configuration for a typical test bench suitable for a high-resolution bandwidth ADC. The most critical element is the sine wave generator (single-tone or multi-tone), where a software-based Direct Digital Synthesizer (DDS) provides complete flexibility, extremely high frequency resolution and clock synchronization performance, utilizing Data acquisition system to perform coherent sampling to avoid leakage and FFT window filtering.

Figure 1. The processing chain of a typical ADC(ac) test setup based on the IEEE 1241 standard. DDFS enables the entire measurement system to be fully digitized, offering several advantages, including complete flexibility and coherent sampling acquisition.

Because the cost is only a fraction of the cost of an audio precision analyzer, it is possible to design a very accurate sine wave generator based on the principle of direct digital frequency synthesis (DDFS), but it needs to be implemented in SHARC by software.^{®}It is implemented on floating-point DSP processors such as processors. A reasonably fast floating-point DSP will be able to meet the real-time requirements, as well as all the algorithms and processing conditions, to achieve the distortion and noise performance levels set by advanced SAR ADCs. Implement NCO phase accumulation using the full-word data length (32-bit or 64-bit fixed-point format) of the SHARC core architecture, perform sine approximation functions using proprietary 40-bit floating-point extended precision, and use digital filters to determine spectral shape , quantization effects (rotation noise and truncation noise) are greatly reduced, which are negligible compared to the disadvantages of digital-to-analog converters (DACs) used for signal reconstruction.

**direct digital frequency synthesis**

In April 1970, Webb filed a patent application for a digital signal generator frequency synthesizer, which described considerations for DDS to generate a variety of analog waveforms, including sine waves, that could be accomplished using just a few digital logic blocks. Later, in early 1971, Tierney et al. published a paper (which later became a frequently cited reference) describing direct digital frequency generation by deepening DDS operations for quadrature generation, as well as the limitations associated with sampling system theory (phase truncation and quadrature generation). frequency planning) problem. The practical applications that followed have mostly relied on discrete standard logic ICs, such as the TTL74xx or ECL10K series. Later in less than 10 years, Stanford Telecom, Qualcomm, Plessey and ADI have introduced fully integrated solutions, such as ADI’s AD9950 and AD9955. These logic ICs are designed to achieve the best balance between speed, power consumption and cost, and their architecture is based on look-up tables (LUTs) to ensure phase-sine amplitude conversion with limited phase, frequency and amplitude resolution. Today, Analog Devices is still the largest and probably the most unique supplier of DDS stand-alone ICs, while current Numerically Controlled Oscillators (NCOs) are often integrated into RF DACs like the AD9164 or AD9174. While these devices have excellent noise and linearity performance across multi-GHz bandwidths, none of them are suitable for testing moderate-speed, high-resolution ADCs such as the LTC2378-20, the AD4020, or the AD7768.

Significant advantages of NCOs and DDSs over traditional PLL-based frequency synthesizers include: extremely high frequency resolution, fast sensitivity, and easy generation of perfectly quadrature sine/cosine waveforms. In addition, a wide bandwidth range and high DC accuracy are available. Its working principle is based on digital signal processing and sampling system theory, and its digital characteristics support fully digital independent control of the phase, frequency and amplitude of the output signal. The block diagram shown in Figure 2 shows the architecture of a traditional DDS, which consists of three functional blocks:

• N-bit phase accumulator;

• Phase-sine-amplitude converter characterised by W-bit truncated phase input word;

• D-bit DAC and its associated reconstruction filter.

Figure 2. The main functional parts of the NCO and its differences from a full direct digital frequency synthesizer, which includes the reconstruction DAC and its associated AAF. The NCO section can be used to test or simulate the DAC.

The phase accumulator is composed of a simple N-bit adder combined with a register. The content of the register is based on the sampling clock F._{CLK}Updated with the input phase increment Δθ (often also referred to as the Frequency Tuning Word, FTW). The accumulator will periodically overflow at the sample or reference clock F_{CLK}and DDS output frequency F_{OUT}between operating like a fractional divider, or operating like a gearbox, the divide ratio is:

The overflow rate provides the output frequency for the generated waveform such that:

where 0≤FTW≤2^{NC1}.The effect of reference or sample fS clock phase noise at the NCO output is reduced due to the divider

The output of the phase accumulator register represents the current phase of the generated waveform. Each discrete accumulator output phase value is then converted to magnitude sine or cosine data or samples by a phase-sine or phase-cosine mapping engine. This function is usually done with trigonometric function values stored in the LUT (ROM), sometimes by performing a sine approximation algorithm, or a combination of the two. The output of the phase-sine-amplitude converter is used by the DAC to generate a quantized and sampled sinusoidal signal before filtering, smoothing the signal and avoiding spectral aliasing. Amplitude quantization due to the limited resolution of the DAC sets theoretical limits on the noise floor and corresponding frequency synthesizer signal-to-noise ratio (SNR). In addition, DACs, as mixed-signal devices, exhibit a range of DC and AC nonlinearities due to their INL, DNL, slew rate, glitches, and settling time, which can generate spurious tones and reduce the overall size of the sine wave generator. Dynamic Range.

The actual sine waveform generator implemented based on the architecture in Figure 2 differs mainly in the phase-amplitude conversion block, which is generally optimized for speed and power consumption rather than high accuracy due to the market orientation of digital radio applications. The easiest way to implement a phase-to-sine-amplitude converter is to use a ROM that stores the sine values in a one-to-one mapping. Unfortunately, the length of the LUT grows exponentially with the width N of the phase accumulator (2^{N}), 2N), and increases linearly with the wavetable data word precision W. Also, the trade-offs and trade-offs between reducing the size of the accumulator or truncating its output can result in reduced frequency resolution and severely degrade SFDR performance. The results show that spurs due to phase or amplitude quantization reduce C6dB/bit. Achieving fine frequency tuning typically requires large N, and several techniques are available to limit the size of the ROM while maintaining adequate spurious performance. Typically a simple compression method is used to reduce the phase amplitude range by a factor of 4 by exploiting the quarter wavelength symmetry of the sine or cosine function. To further narrow the range, truncation of the output of the phase accumulator is actually used, but this results in spurious harmonics. Nonetheless, this approach is widely adopted due to precise frequency resolution requirements, memory size and cost considerations. Various angular decomposition methods are proposed to reduce the memory requirements of LUT-based methods.Combined with amplitude compression using various piecewise, linear, or polynomial interpolation methods, when doing I/Q synthesis that requires sine and cosine functions, accurately estimate the first quadrant of the sine function, or press[0, /4]interval estimation. Likewise, in the absence of a ROM LUT, complex signals can be efficiently generated using angular rotation-based methods by simply calling the displacement and addition operations in a successive approximation method. This approach, typified by the popular CORDIC, is typically faster than when hardware multipliers are not available, or when speed or cost considerations should minimize the number of gate stages required to implement a function (in an FPGA or ASIC). Other methods are faster. Conversely, when hardware multipliers are available (which is always the case in DSP microprocessors), table lookups with interpolation methods and full polynomial computations (e.g. Taylor series expansion, Chebyshev polynomials) are faster than CORDIC, especially When high precision is required.

**High-precision NCO in software**

As the well-known HP analyzer, or as described in application note AN-132, it is not easy to build a high precision AC signal oscillator with equal or better distortion performance than the best analog oscillators, even for audio Spectrum (DC to 20kHz range). However, as mentioned earlier, a full software implementation with sufficient operational precision on the embedded processor to perform the phase calculation (ωt) and the sine function (sin(ωt)) approximation clearly helps to minimize quantization adverse effects, noise and resulting spurs. This means that all NCO functional blocks in Figure 2 are translated into lines of code (not VHDL!), enabling a software version that satisfies real-time constraints to ensure the minimum sampling rate and required frequency bandwidth are achieved.

For the phase-sine-amplitude conversion engine, a full LUT scheme or any variation would require too much memory or too much interpolation to achieve perfect sine consistency. In contrast, polynomial methods for computing sinusoidal approximations allow the use of very low-cost general-purpose DSPs, with a good balance between complexity and precision. Polynomial series expansions are also attractive because of their relative simplicity and the ability to take the chosen type of power series to provide sufficient flexibility and to tune the algorithm to achieve a given precision. It doesn’t require a lot of memory (maybe less than 100 lines of SHARC DSP assembly code), and only a few RAM locations to store polynomial coefficients and variables, since the sine is only calculated at the sample instant.

First, for the sine approximation function, one would obviously choose to use a Taylor/McLaughlin power series with the appropriate order to meet the target accuracy. However, since power series tend to fail at the endpoints, the parameter input must be narrowed down to a smaller interval before any polynomial evaluation can be performed.Without narrowing the parameters, only very high-order polynomials can be used to support in the functional domain (e.g.[C, +]) to achieve high precision. Therefore, some transformations of the elementary functions are required to obtain the required reduction parameters, such as sin(|x|)=sin(f+k×/2) and sin(f)=sin(xCk×/2), where 0f

In addition to periodicity and modulo-2 repetition, the symmetry of the sin(x) function can be used to further narrow the approximation.Given that the sine function is in the interval[0, 2]is asymmetric about the point x=, so the following relation can be used:

narrow down to[0, ].In the same way, sin(x) is in the interval[0, ]symmetric about the line defined by x=/2, so:

x is in the interval[0, /2], which further narrows the approximation of the angle input.By further narrowing the parameter interval (e.g.[0, /4]) to improve accuracy is not an efficient method, as this requires simultaneous estimation of the values of the sine and cosine functions, as shown in the common trigonometric relationship: sin(a+b)=sin(a)×cos(b)+cos(a)× sin(b), which has value in terms of generating quadrature signals.

ADI ADSP-21000 Series Application Note Volume 1 describes a near-ideal (for embedded systems) sine approximation function based on a power series optimization written for the first ADI DSP floating-point processor, the ADSP- 21020, the latter is basically a SHARC core. This implementation of sin(x) relies on the minimax approximation polynomial for floating-point arithmetic published by Hart et al. and refined by Cody and Waite, to reduce round-off errors and avoid the aforementioned cancellation. The minimax method relies on Chebyshev polynomials and the Remitz exchange algorithm to determine the required coefficients for the maximum relative error. MATLAB as shown in Figure 3^{®}As shown, a small change in the setting coefficients can significantly improve the accuracy of the minimax compared to the seventh-order Taylor polynomial.To achieve the best balance of accuracy and speed, the angular input range of this sinusoidal approximation function should be narrowed to[C/2至+/2]interval, and the software program contains an effective range reduction filter, which accounts for about 30% of the total “sine” subroutine execution time.

Figure 3. Unlike the Taylor-McLaughlin method, which is defined around 0, the minmax sine approximation method is[Cπ/2至+π/2]Within the interval, the maximum relative error will be minimized and balanced.

While all calculations can be performed using 32-bit fixed-point arithmetic, for many years the most common and convenient format for mathematical calculations was the IEEE 754 floating-point standard, especially when dealing with long numbers. As a DSP VLSI chip manufacturer, ADI has pioneered the IEEE 754-1985 standard from the start. There were no single-chip floating-point DSP processors at the time, only simple floating-point multipliers and ALU computing ICs such as the ADSP-3212 and ADSP-3222. This format replaced most proprietary formats in the computer industry as the native format for all SHARC DSP processors, with single-precision 32-bit, extended-precision 40-bit, and more recently for the ADSP-SC589 and ADSP-SC573 Double precision 64-bit.

SHARC 40-bit extended single-precision floating-point format with 32-bit mantissa provides sufficient precision for this sine wave generation application (u2^{C32}) , and to help maintain equality, Cody and Waite stated that the overall approximation accuracy of the 15th-order polynomial is 32 bits, in[0至+/2]Errors with uniform distribution in the input domain. To minimize the number of operations and maintain accuracy, the final adjustment is to perform Horner’s Law on polynomial calculations, which is a fast exponentiation method that takes the polynomial value of a point, so:

R1 to R7 are the Cody and Waite coefficients of the polynomial series, requiring only 8 multiplications and 7 additions to calculate any input parameter ε[0, /2]value of the sine function. The complete sin(x) approximation code written as an assembly subroutine executes in about 22 core cycles on a SHARC processor. The original assembly subroutine was changed to perform simultaneous double memory accesses when fetching 40-bit polynomial floating point coefficients to reduce 6 cycles.

The NCO64-bit phase accumulator itself uses the SHARC32-bit ALU in double-precision 2 decimal format when it is executed. The entire phase accumulator execution providing memory updates takes 11 core cycles, so each NCO output sample is generated in about 33 core cycles.

The block diagram in Figure 4 shows the functional block implementation of the software DSP-based NCO, with reference to the arithmetic format precision for each stage. In addition, one or two DACs and their analog antialiasing filter circuits are required to perform analog reconstruction of the signal and implement a complete DDFS. Key elements of the processing chain include:

• 64-bit phase accumulator (SHARC ALU double with overflow);

• 64-bit decimal fixed-point to 40-bit floating-point conversion module;

• Scope reduction module[0至+ /2]and quadrant selection (Cody and Waite);

• Sine approximation algorithm (Hart) for phase-amplitude conversion;

• sin(x) reconstruction and normalization levels in the range C1.0 to +1.0;

• LP FIR filter and sin(x)/x compensation (if necessary);

• And 40-bit floating-point to D-bit fixed-point conversion and scaling functions to match DAC digital inputs.

Figure 4. Simplified block diagram of software DDS showing the format and location of data operations for the various quantization steps between processing units.

An optional digital low-pass filter can be placed at the NCO output to remove spurs and noise that might enter the band of interest. Alternatively, the filter may provide interpolation and/or inverse sin(x)/x frequency response compensation, as determined by the DAC chosen for analog reconstruction. This low-pass FIR filter can be designed using the MATLAB Filter Designer tool. For example, assuming a sampling frequency of 48kSPS, a bandwidth of DC to 20kHz, an in-band ripple of 0.0001dB, and an out-of-band attenuation of -150dB, a high-quality equalized ripple filter with 40-bit floating-point coefficients can be implemented. It has only 99 filter coefficients, and in single instruction single data (SISD) single computational unit mode, the total execution time will consume about 120 SHARC core cycles. After digital filtering, the calculated sample pairs are sent to the DAC by the DMA using one of the DSP synchronous serial ports. For better speed performance, chained DMA operations can also use large ping-pong memory buffers to support block processing operations. For example, the block data size may be equal to the length of the FIR data delay line.

**Achieving the best SFDR, final tuning on NCO**

As mentioned earlier, the primary reason NCOs suffer from spurs is truncation of the phase accumulator output, followed by amplitude quantization for calculated or tabulated sine values. Errors due to phase truncation produce spurs near the carrier frequency through phase modulation (sawtooth), while sinusoidal amplitude quantization causes harmonic-related spurs, but have long been considered random errors and noise. The operation of the phase accumulator is now mathematically explained in depth in a technical paper by Henry T. Nicholas and H. Samueli. Based on the in-depth analysis, a model is proposed that treats the phase accumulator as a discrete phase sample array generator and predicts frequency spurs accordingly.Regardless of the phase accumulator parameters (M, N, W), the length of the phase sequence is equal to

(where GCD is the greatest common divisor), as shown in Figure 4, is determined by the rightmost bit position L of the frequency tuning word M.Thus, the value of L defines the sequence categories, which share their own set of phase components with each other, but according to

Ratio reordering. These truncated phase sample sequences generated in the time domain are used by DFT to determine the respective locations and magnitudes of the spurious lines in the frequency domain. These sequences also show that odd values of M(FTW) show the magnitude of the lowest frequency spurs, and suggest a simple modification of the phase accumulator to meet these minimum degree conditions (just add 1LSB to the FTW). As such, the output sequence of the phase accumulator must always have the same 2N phase elements, regardless of the phase accumulator’s M value and initial contents. After that, the worst spurious tone amplitude level is reduced by 3.922dB, which is equal to SFDR_min(dBc)=6.02×W. The phase accumulator, modified by Nicholas, provides several advantages to the NCO, firstly, it eliminates the situation where the rightmost bit of the FTW is very close to the MSB (frequency sweep in FMCW applications), and secondly, it allows the spurious magnitude to be related to the frequency tuning word M is irrelevant. This modification can easily be achieved by switching the ALU LSB at the sample rate fS, which emulates the same behavior as the phase accumulator if the FTW LSB is set to logic 1. When the phase accumulator size N=64 bits, for the desired frequency F_{OUT}the ½ LSB offset can be considered a negligible error.

Figure 5. The position of the rightmost non-zero bit of the FTW determines the theoretical worst-case level of SFDR. The phase accumulator modified by Nicholas solves the problem of taking any value of N and maximizes the SFDR of the NCO.

With a 32-bit output phase word, W, the maximum spurious amplitude due to phase truncation is limited to C192dBc! Finite quantization of sinusoidal samples also results in another set of frequency spurs, which are usually considered noise and can be obtained using the well-known SNR_{q}(dB)=6.02×D+1.76 formula to estimate. This has to be added to the parasitics, since the approximation error in the phase-sine-amplitude conversion algorithm stage is considered negligible, however, the phase-sine approximation algorithm and computational accuracy must be chosen with great care.

These results show that, on a theoretical level, both the linearity and noise of our software sinusoidal NCO far exceed the thresholds required to test most high-precision ADCs on the market. It still needs to find the last and most critical element in the signal chain: the reconstruction DAC and its complementary analog antialiasing filter and associated driver circuit to meet the desired performance level.

**Refactoring the DAC: The Key!**

A high precision DAC with excellent nonlinear error (INL and DNL) specifications might be chosen first, such as the excellent 20-bit high precision DAC AD5791. But its resolution is only 20 bits, and its R-2R structure does not support performing signal reconstruction, especially to produce very pure sinusoids, because of the large glitches during input transcoding. Traditional DAC architectures are built on binary-weighted current generators or resistor networks and are very sensitive to digital shoot-through and digital switching impairments (such as external or internal timing swings), as well as other switching asymmetries of digital input bits, especially when they cause energy changes. period of major transformation. This creates code-dependent transients that create high-amplitude harmonic spurs.

At resolutions above 20 bits, using an external ultra-linear fast sample-and-hold amplifier doesn’t help much in deglitching the DAC output, as it generates its own transients at tens of LSBs and can be affected by resampling Produces group delay nonlinearity. Signal reconstruction mainly exists in communication applications, by using a segmented architecture (mixing a fully decoded part suitable for the MSB and a binary weighting element suitable for the least significant bit) to solve the glitch problem. Unfortunately, there are currently no commercial DACs with more than 16-bit precision. Unlike the completely predictable behavior of NCOs, DAC errors are difficult to predict and simulate accurately, especially when the manufacturer’s dynamic specifications are small or non-existent, except for DACs or ADCs dedicated to audio applications. Interpolating oversampling and multi-bit DACs seem to be the only solutions. With up to 32-bit resolution, ultra-low distortion and high signal-to-noise ratio, these advanced converters are ideal for signal reconstruction in low to medium bandwidths. To achieve excellent noise and distortion performance in the audio spectrum or slightly wider frequency band (20kHz or 40kHz bandwidth), use the outstanding DAC product in Analog Devices’ product line, the audio stereo DACAD1955, although the resolution is up to 24 bits, this DACs are still very popular audio DACs on the market.

Introduced in 2004, this audio DAC is based on multi-bit-modulator and oversampling techniques, combined with various tricks to mitigate distortion and other problems inherent in this conversion itself.

Even now, the interpolating LP FIR filter employed by the AD1955 is still the best in its class. It has extremely high stopband attenuation (C120dB) and extremely low in-band ripple (±0.0001dB). Its two (left and right channel) DACs can operate at speeds up to 200kSPS, but achieve the best ac performance at 48kSPS and 96kSPS, and its dynamic range, as well as SNR in stereo mode, supports typical EIAJ standards, A Weighted 120dB factor. In mono mode, the two channels are combined out of phase at the same time, promising a 3 dB improvement in performance. However, for wideband applications, these specifications are less practical because they are synthetic and have bandwidths ranging from 20Hz to 20kHz. Out-of-band noise and spurs will not exceed 20kHz, in part because of EIAJ standards, A-weighted filters, and audio industry specification definitions. This bandpass filter, tailored to specific audio measurement requirements, simulates the frequency response of the human ear and provides a 3dB improvement in performance compared to unfiltered measurements.

**DDFS Hardware Demonstration Platform**

The complete DDFS is implemented using two evaluation boards, one supporting the DSP processor and one suitable for analog signal reconstruction using the AD1955DAC. The Gen 2 SHARCADSP-21161N evaluation board was chosen for its usability, ease of use, and thin configuration for any audio application. The ADSP-21161N, which is still in mass production, was designed not long ago to support industrial high-end consumer electronics and professional audio applications, offering up to 110Mips and 660MFlops, or 220MMACS/s capacity. Compared with the latest generation SHARC processors, the biggest difference of the ADSP-21161N is that it uses a shorter 3-level instruction pipeline, an on-chip 1Mb three-port RAM, and a smaller number of peripherals. The last and most critical stage of the precision tone generator is based on the AD1955 evaluation board, which must reconstruct the analog signal in a fully restored fashion from the samples provided by the software NCO. This evaluation board features an anti-aliasing filter (AAF) that optimizes the audio bandwidth to meet the Nyquist standard, and in addition to the usual S/PDIF or AES-EBU receivers, two serial audio interfaces for supporting PCM/I

^{2}S and DSD digital streams. PCM/I

^{2}The S serial link connector is used to connect the AD1955DAC board to the serial port 1 and 3 connectors (J) of the ADSP-21161NEVB. Both boards can be configured to use I

^{2}S PCM or DSP mode, running at 48kSPS, 96kSPS or 192kSPS sample rate. DSP serial port 1 generates the left and right channel data, word select or left/right frame sync, and the SCK bit clock signal required by the digital input interface of the dual frequency DAC. Serial port 3 is only used to generate the DAC master clock MCLK needed to run the DAC interpolation filter and – the modulator, which operates at 256 times (default) faster than the input sampling frequency (48kSPS). Since all DAC clock signals are generated by the DSP, the CCHD-957, an ultra-low noise oscillator provided by Crystek, was used to replace the board’s original low-cost Epson clock oscillator. Its phase noise can be as low as C148dB/Hz at 1kHz for a 24.576MHz output frequency.

On the analog output side, an active I/V converter must be used to maintain the AD1955 current differential output at a constant common-mode voltage (typically 2.8V) to minimize distortion. Ultra-low distortion and ultra-low noise precision op amps like the AD797 meet this need and can also be used to handle analog signal reconstruction. Since the two differential outputs are processed separately by the DSP, a stereo output configuration with AAF topology was chosen instead of a mono mode. This AAF uses LTspice^{®}XVII is simulated, and the results are shown in Figure 6. Since the last part of the filter is passive, an active differential buffer stage should be added like the recently introduced ADA4945. This fully differential amplifier with low noise, ultra-low distortion, and fast settling time is a near-perfect DAC accessory for driving any high-resolution SAR and -ADC. The ADA4945 has a relatively large common-mode output voltage range and excellent DC characteristics, which provide excellent output balance and help reject even-order harmonic distortion products.

Figure 6. LTspice simulates the frequency response of the AD1955 EVB third-order antialiasing filter (stereo configuration).

The EVB third-order filter has a C3dB cutoff frequency of 76kHz and only attenuates C31db at 500kHz. This low-pass filter has excellent in-band flatness, but out-of-band attenuation must be greatly improved, even for purely reconstructed audio applications. This is necessary to suppress the DAC shaping noise and the modulator clock frequency MCLK. Depending on the specific use of the software DDS, for a single-signal tone generator or an arbitrary waveform generator (AWG when generating complex waveforms), the AAF must be optimized to account for out-of-band attenuation or group delay distortion. Taking the familiar SRS DS360 ultra-low distortion function generator as an example for comparison, a 7th-order Cauer AAF can achieve a similar sampling rate. Signal reconstruction is done by the AD1862, a serial-input 20-bit segmented R-2R DAC for digital audio applications. AD1862 at up to 768kHz (×16f_{S}) frequency can maintain a 20-bit word sampling rate with excellent noise and linearity. It supports single-ended current output, so the best amplifiers can be used for external IV conversion.

The AD1955 and SHARC DSP combination was tested against several high-resolution SAR ADCs, such as the AD4020, with no external optional passive filters. By default, the base AD4020 evaluation board has no options other than the onboard ADA4807 driver. A simple circuit for biasing the ADC inputs at a common-mode voltage of V_REF/2 provides a fairly low 300 Ω input impedance, requiring the use of signal isolation, AC coupling, or the use of an external differential amplifier module such as the EVAL-ADA4945-1. The AD4020 reference design board described in Circuit Note CN-0513 is a good choice. It contains a discrete programmable gain instrumentation amplifier (PGIA) that provides high input impedance and supports ±5 V differential input signals (G=1). Although these AD4020 boards and their SDP-H1 controllers do not support coherent sampling acquisition, they have excellent sample waveform capture lengths of up to 1M. As a result, FFTs with selectable windows can be implemented, providing excellent frequency resolution and a low noise floor. For example, for a 7-term Blackman-Harris window, the 1Mpts FFT plot shown in Figure 7 depicts the AD1955’s distortion level at the resulting 990.059Hz sine wave. The second harmonic is the largest distortion component and largest spur at C111.8dBc in the 350 kHz bandwidth. However, when considering the entire 806kHz ADC Nyquist bandwidth, the SFDR is limited by the -DAC modulator, interpolation filter frequency, and its second harmonics (384 kHz and 768 kHz).

Figure 7. The 1 M-point FFT analysis shows good distortion performance below C111dBc, with maximum spurs in the 10kHz to 200kHz band at 1kHz input frequency. The noise floor is about C146dBFS.

A conventional AD1862 was tested under the same conditions and showed slightly different frequency behavior. In the differential configuration, the clock speed of the two 20-bit DACs is approximately 500kSPS, the noise floor is C151dBFS at 1.130566kHz, and the THD at a sinusoidal output level of 12 V pp is C104.5dB. At the AD4020Nyquist bandwidth (806 kHz), the SFDR is close to 106dB, limited by the third harmonic. The DAC reconstruction filter is based on two AD743 low-noise FET amplifiers and is a third-order filter like the filter in the AD1955 evaluation board, but with a cutoff frequency of 35kHz at -3dB.

To be effective, a DDS-based generator needs to employ a decent filter that supports greater than 100dB attenuation at about 250kHz to generate DC up to the 25kHz CW signal frequency range. This can be achieved using a sixth-order Chebyshev filter, or even a sixth-order Butterworth low-pass filter that exhibits excellent in-band flatness. The filter order will be minimized to limit the number of analog stages and problem points such as noise and distortion.

**in conclusion**

Preliminary and out-of-the-box tests performed on standard evaluation boards show that processor-based DDS technology for traditional sine wave CW generation is just around the corner to achieve high performance. With careful design of the reconstruction filter and analog output buffer stage, a C120dBc harmonic distortion factor can be achieved. DSP-based NCO/DDS are not only limited by single-tone sine wave generation. By using an optimized AAF (Bessel or Butterworth) with a suitable cutoff frequency and no other hardware changes, the same combination of DSP and DAC can be used as a high-performance AWG to generate any type of waveform, e.g. a full synthesis can Set up parametric multi-tone sine waves (with full control over the phase and amplitude of each component) to perform IMD testing.

Since floating-point arithmetic is critical for applications requiring high accuracy and/or high dynamic range, today, the low-cost ADSP-21571 or SoCADSP-SC571 (ARM^{®} and SHARC) and other SHARC+DSP processors are actually the industry’s real-time processing standards, supporting a total sampling rate of up to 10MSPS. The dual SHARC cores and their hardware accelerometers are clocked at 500MHz to provide more than 5Gflops of computing performance and dozens of internal dedicated SRAMs, which are essential components for generating various waveforms and implementing complex analytical processing. Such applications demonstrate that the systematic use of hardware programmable solutions is not necessary when implementing precise digital signal processing. Thanks to ADI’s CCES, VDSP++ C and C++ compilers, as well as a full suite of emulators and real-time debuggers, floating-point processors and their entire development environment can quickly and easily port code from emulators such as MATLAB, as well as quickly implement debugging.

The Links: **PM50RLA120** **VUB72-16NO1** **TIMMALCD**