Cadence accelerates development with Helium Virtual and Hybrid Studio

Cadence accelerates development with Helium Virtual and Hybrid Studio

Cadence accelerates development with Helium Virtual and Hybrid Studio

Cadence Design Systems has announced the introduction of the Helium Virtual and Hybrid Studio, a platform that’s intended to accelerate the creation of virtual and hybrid prototypes of complex systems.

The Helium Studio will enable early software bring-up for hardware-software co-verification and co-debug, and provides comprehensive support for platform assembly, enabling the creation and debug of virtual models and offers a rich library of pre-built virtual models and hybrid adapters.

Using the system, verification with a virtual or hybrid model of the SoC is both orders of magnitude faster than verification with a pure RTL model, but enables early software bring-up before the RTL is available.

Architected to natively integrate with the Cadence verification engines, including the Palladium Z2 Enterprise Emulation Platform, the Protium X2 Enterprise Prototyping Platform and Xcelium Logic Simulator, the Helium Studio is able to accelerate system development by verifying embedded software/firmware on pure virtual and hybrid configurations even when the RTL is not ready.

Engineers creating next-generation designs, including for mobile, automotive and hyperscale computing applications, need to validate software on a pre-silicon platform to ensure design success and to meet time-to-market schedules. The Helium Studio will allow designers to build high-quality virtual and hybrid SoC models. Through the native integration of the runtime software engine with the Helium Studio, the Palladium Z2 platform and the Protium X2 platform, the Helium Studio is able to provide a uniform debug experience from virtual model to RTL for software designers.

The Helium Studio features:

Virtual studio: The system allows GUI-based platform assembly for quick and correct-by-construction platform creation, enabling early software bring-up. Once the platform is assembled, the virtual studio can be used to execute and debug the software stack and the hardware design.

Hybrid studio: Designers will be able to create hybrid configurations quickly using a rich library of hybrid adapters, transactors and smart memory that optimise communication channels for maximum throughput and are natively integrated in the Palladium and Protium platforms. The new gearshift technology allows users to hot-swap their software bring-up from virtual to RTL, providing high speed when it is needed and high accuracy on the RTL engines when necessary.

Virtual model library: The system offers a comprehensive virtual model library featuring the latest Arm technology model portfolio, which includes support for Armv9-A, in which designers can access multiple reference and starter virtual and hybrid platforms that are ready to boot on the latest Linux and Android operating systems, accelerating bring-up time for new platforms.

Embedded software debug: The system offers uniform and comprehensive multi-core, multi-process debug of embedded software, allowing designers to have greater control and visibility into the software through use of a single debugger that works with software running on virtual platforms and RTL platforms simultaneously. The native integration of the software engine with the virtual and RTL runtime engines enables synchronized hardware-software debug.

“Validating embedded software concurrently with RTL and earlier in the development process is critical to ensuring the success of next-generation mobile, automotive and hyperscale SoC designs,” said Paul Cunningham, senior vice president and general manager of the System & Verification Group at Cadence. “Our Helium Studio takes advantage of our best-in-class verification engines, including the Palladium and Protium dynamic duo, to enable fast software development and benchmarking for power and performance validation. This new system provides designers with a unified platform that accelerates overall verification throughput.”

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