“The overall accuracy of a high-resolution, successive-approximation ADC depends on the accuracy, stability, and drive capability of its reference. The switched capacitors at the ADC reference input are dynamically loaded, so the reference circuit must be able to handle currents that are time and throughput rate dependent. Some ADCs have an on-chip reference and reference buffer, but these devices may not be optimal in terms of power consumption or performance—the best performance is usually achieved with an external reference circuit. This article discusses the challenges and requirements encountered in reference circuit design.

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The overall accuracy of a high-resolution, successive-approximation ADC depends on the accuracy, stability, and drive capability of its reference. The switched capacitors at the ADC reference input are dynamically loaded, so the reference circuit must be able to handle currents that are time and throughput rate dependent. Some ADCs have an on-chip reference and reference buffer, but these devices may not be optimal in terms of power consumption or performance—the best performance is usually achieved with an external reference circuit. This article discusses the challenges and requirements encountered in reference circuit design.

**Reference voltage input**

A simplified schematic of the successive approximation ADC is shown in Figure 1. During the sampling interval, the capacitive DAC is connected to the ADC input and a charge proportional to the input voltage is stored in the capacitor. After the conversion begins, the DAC is disconnected from the input. The conversion algorithm switches each bit one by one to the reference voltage or ground. Charge redistribution across the capacitor can cause current to flow into or out of the voltage reference. The dynamic current load is a function of the ADC throughput rate and the internal clock for control bit verification. The most significant bit (MSB) holds most of the charge and requires most of the current.

Figure 1. Simplified schematic of a 16-bit successive-proximity ADC

Figure 2 shows AD7980, 16-bit, 1 MSPS, PulSAR^{®}Dynamic current load at the reference input of successive approximation ADCs. The measurement is obtained by observing the voltage drop across the 500 Ω resistor between the reference and the reference pin. The curves show current spikes up to 2.5 mA with smaller spikes distributed throughout the transition.

Figure 2. AD7980 Dynamic Reference Current

To support this current while maintaining the noise-free nature of the reference, place a high value, low ESR storage capacitor, typically 10 µF or greater, as close as possible to the reference input. Larger capacitors will further smooth the current load and reduce the burden on the reference circuit, but very large capacitors can create stability problems. The reference must be able to supply the average current required to fill the reference capacitor without causing the reference voltage to drop too much. In ADC data sheets, the reference input current average is usually specified at a specific throughput rate. For example, in the AD7980 data sheet, the average reference current of a 5 V reference at 1 MSPS is specified as 330 µA typical. No current is consumed between conversions, so the reference current scales linearly with throughput, dropping to 33 µA at 100 kSPS. The reference—or reference buffer—must have an output impedance low enough at the highest frequency of interest to maintain the voltage level at the ADC input so that the voltage does not drop too much due to the current.

**Voltage Reference Output Drive**

Figure 3 shows a typical reference circuit. The reference can integrate a buffer with sufficient drive current, or an appropriate op amp can be used as the buffer. To avoid conversion errors, the average current required at a given throughput rate should not drop the reference voltage by more than ½ LSB. This error is most pronounced in burst transitions, as the reference load will vary from zero to the average reference current at this throughput rate.

Figure 3. Typical Precision Successive Approximation ADC Reference Circuit

AD7980 is a 16-bit ADC, its I_{REF} = 330 µA , V_{REF} = 5 V; using this ADC as an example to determine if the reference has sufficient drive capability, the maximum allowable output impedance for ½ LSB drop is:

Most voltage references do not specify output impedance, but do specify load regulation, usually expressed in ppm/mA. Multiply it by the reference voltage and divide by 1000 to convert to output impedance. For example, “ADR435 Ultralow Noise XFET^{®} The 5-V 5 V reference is specified with a maximum load regulation of 15 ppm/mA when sourcing current. Converted to resistance, we get:

So in terms of output impedance, the ADR435 should suffice. It can draw a maximum current of 10 mA, which is enough to handle an average reference current of 330 µA. When the ADC input voltage exceeds the reference voltage, even for a short period of time, it will inject current into the reference voltage source, so the reference voltage source must be able to draw a certain amount of current. Figure 4 shows the diode connection between the ADC and the reference input, which can cause current to flow into the reference during an input overrange condition. Unlike some older references, the ADR435 can sink 10 mA.

Figure 4. AD7980 Analog Input Structure

Since the parameter requirement of the reference current is linear with the throughput rate, lower throughput rate or use a lower throughput ADC such as 500 kSPSAD7988-5 or 100 kSPSAD7988-1 (I_{REF} = 250 µA), a higher output impedance (lower power dissipation) reference can be used. By reducing the reference current, the maximum output impedance can be calculated. Note that these formulas are only guidelines, and the hardware drive capability must be tested for the selected reference.

Reference buffers can be used when the selected reference has insufficient drive capability, or when a micropower reference is preferred. This can be achieved by configuring the appropriate op amp for unity gain. The op amp must have low noise, proper output drive capability, and be stable with large capacitive loads. It must also be able to supply the required current. The output impedance of an op amp is usually not specified, but can generally be determined from a plot of output impedance versus frequency, as shown in Figure 5 for the AD803180 MHz rail-to-rail op amp.

Figure 5. AD8031ROUT vs. Frequency

Below 100 kHz, the output impedance is below 0.1 Ω; at dc, it is below 0.05 Ω, so it is a good choice for our example of driving the AD7980 at 1 MSPS. Maintaining low output impedance over a wide frequency range is important for driving reference voltage inputs. Even with larger capacitance values, the storage capacitor can never eliminate the current drawn by the reference input. The frequency content of the current ripple is a function of the throughput rate and the bandwidth of the input signal. The large storage capacitor handles the high frequency currents associated with the throughput rate, and the reference buffer must be able to maintain a low impedance at the maximum input signal frequency (or the frequency at which the storage capacitor impedance becomes low enough to provide the required current). Typical curves in reference data sheets show output impedance versus frequency and should be considered when selecting a reference.

A good choice is the AD8031, which is stable for capacitive loads greater than 10 µF. Other op amps such as the ADA4841 are also stable with large capacitors as they primarily drive stable DC levels, but some specific op amps must be tested to determine the loading characteristics. It is not a good idea to use a series resistor before the capacitor for stability , as this increases the output impedance.

Reference buffers are useful when driving multiple ADCs from a single reference, such as in the simultaneous sampling application shown in Figure 6.

Figure 6. Reference circuit driving multiple ADCs

All ADC reference inputs have their own storage capacitors, placed as close as possible to the reference input pins. Each trace from the reference input is routed back to the star connection at the output of the reference buffer to minimize crosstalk effects. Reference buffers with low output impedance and high output current capability can drive many ADCs, depending on current requirements. Note that the buffer must be stable with additional capacitance associated with multiple reference capacitors.

**Noise and Temperature Drift**

Once the drive capability is determined, it must be ensured that the noise of the reference circuit does not affect the ADC performance. To maintain signal-to-noise ratio (SNR) and other specifications, the reference noise contribution must be limited to a fraction of the ADC noise (ideally 20% or less). The AD7980 integrates a 5 V reference with a specified SNR of 91 dB. Convert to rms to get:

Therefore, the reference circuit should have no more than 10 µV rms of noise to minimize the impact on SNR. Noise specifications for references and op amps can generally be broken down into two parts: low-frequency noise (1/f) and broadband noise. Combining these two parts yields the total noise contribution of the reference circuit. Figure 7 shows a typical noise versus frequency plot of the ADR4311 2.5 V reference.

Figure 7. ADR431 Noise Curve with Compensation Network

The ADR435 compensates its internal op amp, drives large capacitive loads and avoids noise peaking, making it ideal for use with ADCs. A more detailed description can be found in the data sheet. With 10 µF capacitors, it has a noise rating of 8 µV pp 1/f (0.1 Hz to 10 Hz) and a broadband noise spectral density of 115 nV/√Hz. The estimated noise bandwidth is 3 kHz. To convert 1/f noise from peak-to-peak to root mean square (rms), divide by 6.6:

Then, use the estimated bandwidth with the 10 µF capacitor to calculate the broadband noise contribution. The effective bandwidth is determined by:

Use this effective bandwidth to calculate the rms broadband noise:

The total rms noise is the root sum of the squares of the low frequency noise and the broadband noise:

The result is less than 10 µV rms, so it doesn’t affect the ADC’s SNR much. These calculations can be used to estimate the noise contribution of the voltage reference to judge its stability, but the data needs to be verified using real hardware on a bench.

If the buffer is used after the reference, the same analysis can be used to calculate the noise contribution. For example, the AD8031 has a noise spectral density of 15 nV/√Hz. Due to the 10 µF capacitor at the output, its measurement bandwidth drops to approximately 16 kHz. Using this bandwidth and noise density, while ignoring 1/f noise, the noise contribution is 2.4 µV rms. An estimate of the total noise is obtained by taking the root sum of the squares of the reference buffer noise and the reference noise. Typically, the noise density of the reference buffer is much lower than the reference noise density.

When a reference buffer is used, the noise from the reference can be bandwidth limited by adding an RC filter with a very low cutoff frequency at the reference output, as shown in Figure 8. This can be very efficient, given that the reference is often a major source of noise.

Figure 8. Reference with RC Filtering

Some other important considerations when choosing a voltage reference include initial accuracy and temperature drift. The initial accuracy is in % or mV. Many systems allow calibration, so initial accuracy is not as important as drift, which is usually measured in ppm/°C or µV/°C. Most good references drift below 10 ppm/°C, and the ADR45xx family drives drift to just a few ppm/°C. This drift must be factored into the system error budget.

**Troubleshooting the Voltage Reference**

A poorly designed reference circuit can cause severe conversion errors. The most common reference problems are repetitive or “sticky” code problems from the ADC. When there is enough noise at the input of the reference, it may cause the ADC to make incorrect bit judgments. Even if the input changes, it repeats the same code multiple times, or fills the lower significant bits with a repeated string of 1s or 0s, as shown in Figure 9. In the red circle area, the ADC is stuck and returns the same code repeatedly. Usually the problem near full scale is more serious, because the reference noise has a greater impact on the judgment of the more significant bits. Once a wrong bit judgment is made, the remaining bits are filled with 1 or 0.

Figure 9. “Glue” code in ADC transfer function

The most common causes of “stuck” bits are the size and location of the reference capacitors, insufficient drive capability of the reference/reference buffer, or excessive reference/reference buffer selection noise.

It is important to place the storage capacitor close to the ADC’s reference input pins and use wide traces for the connection, as shown in Figure 10. Use multiple vias to connect the capacitor to the ground plane for a lower impedance path. If the reference has a dedicated ground, the capacitor should be connected near this pin with a wide trace. Since the capacitor acts as a charge bank, it must be large enough to limit attenuation and must have low ESR characteristics. Ceramic capacitors with X5R dielectric are a good choice. Capacitors are typically in the 10 µF to 47 µF range, but depending on the ADC’s current requirements, smaller values are sometimes used.

Figure 10. Typical Reference Capacitor Layout

Insufficient drive capability is another issue, especially with low-power references or micro-power reference buffers, as these typically have much higher output impedances that increase significantly with frequency. This problem is especially pronounced when using ADCs with higher throughput rates, since the current requirements are higher at lower throughput rates.

Excessive noise from the reference or reference buffer is related to the LSB size of the converter and can also cause sticky codes, so the voltage noise of the reference circuit must be kept to a fraction of the LSB voltage.

**in conclusion**

This article discusses how to design reference circuits for precision successive approximation ADCs and highlights how to troubleshoot some common problems. The formulas in this paper are used to estimate the drive capability and noise requirements of the reference circuit so that there is a higher probability that the circuit will pass the hardware test.

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