This ADC breaks the design difficulties of precision data acquisition signal chain

【Introduction】Many applications require a precision data acquisition signal chain to digitize analog data for accurate data acquisition and processing. Precision system designers are under increasing pressure to find innovative ways to increase performance and reduce power consumption while accommodating higher circuit densities on small PCB circuit boards. The purpose of this article is to discuss common challenges encountered in precision data acquisition signal chain design and how to address these challenges with a new generation of 16-bit/18-bit, 2 MSPS, precision successive approximation register (SAR) ADCs. The AD4000/AD4003 (16-bit/18-bit) ADC is designed based on ADI’s advanced technology, integrates a variety of easy-to-use features, and has a variety of system-level advantages to help reduce signal chain power consumption and reduce signal chain complexity performance, increasing channel density while also increasing performance levels. This article will focus on data acquisition subsystem performance and design challenges, illustrating how this ADC family can have application-level impact in multiple end markets.

Common Signal Chain Design Difficulties

Figure 1 shows a typical signal chain used when building a precision data acquisition system. Applications requiring sophisticated data acquisition systems, such as automated test equipment, machine automation, and industrial and medical instrumentation, exhibit common trends that are often considered technically conflicting. For example, system designers are forced to compromise on performance to maintain tight system power budgets, or to reserve a small area on the board to achieve high channel density. System designers of these precision data acquisition signal chains face common challenges on several fronts: driving SAR ADC inputs; protecting ADC inputs from overvoltage events; reducing system power consumption with a single supply; Microcontrollers and/or digital isolators for higher system throughput, etc.

This ADC breaks the design difficulties of precision data acquisition signal chain

Figure 1. Typical Precision Data Acquisition Signal Chain

Driven by high-resolution precision SAR ADCs has always been a thorny problem due to the switched-capacitor input structure. System designers need to pay close attention to the ADC driver data sheet for specifications such as noise, distortion, input/output voltage headroom/headroom, bandwidth, and settling time. Typically, high-speed ADC drivers are used that require wide bandwidth, low noise, and high power to settle the switched-capacitor kickback of the SAR ADC input within the available acquisition time. This requirement drastically reduces the choice of amplifiers available to drive the ADC, necessitating significant performance/power/area compromises. In addition, choosing an appropriate RC filter to place between the driver and the ADC input imposes further constraints on amplifier selection and performance. An RC filter is required between the ADC driver output and the SAR ADC input to limit broadband noise and reduce the effects of charge kickback. Typically, the system designer spends a lot of time evaluating the signal chain to ensure that the chosen ADC driver and RC filter can actually drive the ADC to achieve the desired performance.

In power-sensitive applications such as battery-operated instrumentation, a low-voltage single supply is often required to operate the system. This minimizes the power dissipation of the circuit, but creates headroom and headroom issues for the amplifier front end. This means that the full range of the ADC input may not be available because the driving amplifier cannot drive all the way to ground, nor all the way to the upper end of the ADC input range, resulting in reduced overall system performance. This situation can be compensated for by increasing the supply voltage, but at the cost of increased power consumption or reduced dynamic range performance of the system.

Most ADC analog inputs (IN+ and IN−) do not have overvoltage protection circuits other than ESD protection diodes. In applications where the amplifier rails are greater than VREF and less than ground, it is possible for the output to exceed the input voltage range of the device. During an overvoltage event, the ESD protection diode between the two analog input (IN+ or IN−) pins connected to REF forward biases and shorts the input pin connected to REF, potentially overloading the reference, cause device damage, or interfere with a reference that is shared among multiple ADCs. As a result, protection circuits such as Schottky diodes need to be added to the ADC inputs to prevent overvoltage conditions from damaging the ADC. Unfortunately, Schottky diodes can add distortion and other errors due to leakage current.

Precision applications have different requirements in terms of the processor that interfaces with the ADC. For safety reasons, some applications require the use of a galvanic isolation mechanism and use a digital isolator between the ADC and the processor for this purpose. This processor selection and isolation requirements place constraints on the efficiency of the digital interface used to interface with the ADC. Typically, low-end processors/FPGAs or low-power microcontrollers have lower serial clock rates. This can result in lower ADC throughput than expected due to long ADC conversion delays before outputting the conversion results. Digital isolators can also limit the maximum serial clock rate that can be achieved across the isolation barrier, as the propagation delay in the isolator can limit ADC throughput. In these cases, it is best to use an ADC that can achieve higher throughput rates without significantly increasing the serial clock rate.

AD4000/AD4003 Precision SAR ADCs

The AD4000/AD4003 series are fast, low-power, single-supply, 16-bit/18-bit precision ADCs based on the SAR architecture that uniquely combine high performance with ease of use to reduce system complexity and simplify the signal chain BOM, and drastically reduce time to market (see Figure 2). With this family, designers can solve the system-level technical challenges of precision data acquisition systems without making major compromises. For example, features such as longer acquisition times left to the user, high input impedance (Z) mode, and span compression mode are combined in the AD4000/AD4003 ADC family to reduce the challenges associated with ADC driver stage design and increase the flexibility of ADC driver selection sex. This reduces overall system power consumption, increases density, and shortens customer design cycles. Most of the easy-to-use features can be enabled/disabled by writing to the configuration registers via the SPI interface. Note that the AD4000/AD4003 ADC family is pin compatible with the 10-lead AD798x/AD769x ADC family.

This ADC breaks the design difficulties of precision data acquisition signal chain

Figure 2. Key Benefits of AD4000/AD4003 ADCs

long acquisition phase

The AD4000/AD4003 ADC has a shorter conversion time of 290 ns, and the ADC returns to the acquisition phase 100 ns before the end of the current conversion process. The SAR ADC cycle time consists of a conversion phase and an acquisition phase. During the conversion phase, the ADC capacitor DAC is disconnected from the ADC input to perform the SAR conversion. The input is reconnected during the acquisition phase, and the ADC driver must settle the input to the correct voltage before the next conversion phase begins. A longer acquisition phase reduces the settling requirements for the driver amplifier and allows for a lower RC filter cutoff frequency, which means that higher noise and/or lower power/bandwidth amplifiers can be used. Larger R values ​​and smaller corresponding C values ​​can be used in the RC filter to reduce amplifier stability issues without significantly impacting distortion performance. A larger value of R helps protect the ADC input from overvoltage conditions; it also reduces dynamic power dissipation in the amplifier.

High Input Impedance Mode

To achieve the high-quality performance listed in the high-resolution precision SAR ADC data sheets, system designers often have to use dedicated high-power, high-speed amplifiers to drive the traditional switched-capacitor SAR ADC inputs in their precision applications. This is one of the difficulties often encountered in the design of precision data acquisition signal chains. The advantage of high-Z mode is that it supports low input current at slow (<10 kHz) or DC-like signal conditions, and enables higher distortion (THD) performance in the input frequency range up to 100 kHz.

The AD4000/AD4003 ADCs integrate a high-Z mode to reduce nonlinear charge kickback when the capacitive DAC switches back to the input at the start of the acquisition. When high-Z mode is enabled, the capacitor DAC is charged at the end of the conversion to hold the last sampled voltage. This process reduces any nonlinear charge effects of the conversion process that would affect the voltage sampled at the ADC input before the next sample.

Figure 3 shows the input current of the AD4000/AD4003 ADC with high-Z mode enabled/disabled. The low input current makes the ADC easier to drive than conventional SAR ADCs available on the market, even when high-Z mode is disabled. If you compare the input current with high-Z mode disabled in Figure 3 to the input current of the previous generation AD7982 ADC, the AD4003 has reduced the input current by a factor of 4 at 1 MSPS. When high-Z mode is enabled, the input current is further reduced to sub-microamps. High-Z mode should be disabled when input frequencies exceed 100 kHz, or when multiplexing inputs.

With the reduced input current of the AD4000/AD4003 ADCs, it can be driven with a much higher source impedance than conventional SARs. This means that the resistor values ​​in the RC filter can be 10 times larger than in traditional SAR designs.

This ADC breaks the design difficulties of precision data acquisition signal chain

Figure 3. AD4003 ADC Input Current vs. Input Differential Voltage in High-Z Enable/Disable Condition

As shown in Figure 4, the AD4000/AD4003 ADCs allow the ADC to be driven with a variety of low-power/bandwidth precision amplifiers with RC filters with lower cutoff frequencies, eliminating the need for dedicated high-speed ADC drivers and reducing precision low System power, size, and cost for bandwidth applications (signal bandwidth < 10 kHz). Ultimately, the AD4000/AD4003 allow the selection of amplifiers and RC filters before the ADC based on the signal bandwidth of interest rather than the settling requirements of the switched capacitor SAR ADC input.

This ADC breaks the design difficulties of precision data acquisition signal chain

Figure 4. Traditional Precision Signal Chain

Figure 5 and Figure 6 show the SNR and THD performance of the AD4003 ADC when driving the AD4003 ADC at full speed throughput of 2 MSPS with high Z enabled/disabled and various RC filter values ​​using is the ADA4077 (IQUIESCENT = 400 µA/amp), ADA4084 (IQUIESCENT = 600 µA/amp),

ADA4610 (IQUIESCENT = 1.5 mA/amp) precision amplifier. With high Z enabled at 2.27 MHz RC bandwidth and 1 kHz input signal, these amplifiers achieve typical SNR of 96 dB to 99 dB and typical THD better than –110 dB. When high-Z mode is enabled, even at R values ​​greater than 200 Ω, the THD is improved by about 10 dB. Even at the ultra-low RC filter cutoff frequency, the highest SNR is close to 99 dB.

With high Z enabled, the ADC consumes about 2 mW/MSPS of additional power, but this is still significantly lower than when using a dedicated ADC driver such as the ADA4807-1, saving PCB area and bill of materials . For most systems, the front end typically limits the overall AC/DC performance that the signal chain can achieve. As can be seen from the selected precision amplifier data sheets in Figures 5 and 6, the noise and distortion performance of the precision amplifier itself dominates the SNR and THD specifications at a certain input frequency. However, the AD4003 ADC with high-Z mode can greatly increase the choice of driver amplifiers, including precision amplifiers used in signal conditioning stages, while also increasing the flexibility of RC filter selection. For example, when the AD4003 ADC high Z is enabled and a 4.42 MHz wideband input filter is used with the ADA4084-2 driver amplifier, the SNR performance is about 95 dB. If the ADC driver noise is strongly filtered with a 498 kHz filter, the SNR can be improved by 3 dB to 98 dB. The degraded SNR performance of the AD7982 ADC at lower RC cutoff frequencies is due to the fact that the ADC input is not kickbacked for the shorter acquisition time.

This ADC breaks the design difficulties of precision data acquisition signal chain

Figure 5. SNR vs. RC Bandwidth Using the ADA4077, ADA4084, and ADA4610 Precision Amplifiers

This ADC breaks the design difficulties of precision data acquisition signal chain

Figure 6. THD vs. RC Bandwidth Using the ADA4077, ADA4084, and ADA4610 Precision Amplifiers

Figure 7(a) shows that a system designer can use the ADA4077, a 2.5x lower power ADC driver (compared to the ADA4807), and with the high-Z mode disabled, the AD4003 ADC still achieves a SINAD of about 97 dB (3 dB higher than the AD7982 ADC). ). Even if the RC bandwidth is increased to 2.9MHz, the ADA4077 amplifier cannot directly drive the AD7982 ADC with good performance. If strongly filtered with a lower RC bandwidth cutoff frequency, the driver cannot remove the ADC kickback within the available acquisition time, and the ADC SINAD performance is degraded. When high-Z mode is disabled or enabled, the AD4003 ADC has significantly reduced switched capacitor kickback and 2.5 times longer acquisition time at 1 MSPS, so its SINAD performance is still significantly better than the AD7982 ADC.

Using two ADC drivers at a lower RC filter cutoff frequency when high Z mode is enabled, the AD4003 ADC has better SINAD performance, which helps eliminate more signal from upstream when the signal bandwidth of interest is lower component broadband noise. When high-Z mode is not enabled, there is a tradeoff between the RC filter cutoff frequency and SINAD performance.

This ADC breaks the design difficulties of precision data acquisition signal chain

Figure 7. Comparison of AD4003 ADC and AD7982 ADC Amplifier Drivers Using the ADA4077 and ADA4807: SINAD vs. RC Bandwidth with High-Z Mode Disabled and Enabled (FS = 1 MSPS, fIN = 1 kHz).

span compression

The AD4000/AD4003 ADCs integrate a span compression mode that is useful for systems that use only a single supply to power the SAR ADC driver. This mode eliminates the negative power supply requirement for the ADC driver, while maintaining the full resolution of the ADC, reducing power consumption and reducing power supply design complexity. As shown in Figure 8, the ADC performs digital scaling, mapping zero-scale codes from 0 V to 0.1 V × VREF, and full-scale codes from VREF to 0.9 × VREF. In the reduced input range, the SNR of the AD4000/AD4003 ADC is about ~1.9dB (20*log(4/5)). For example, for a subsystem using a single 5 V supply with a typical reference voltage of 4.096 V, the full-scale input range is ~0.41 V to 3.69 V, providing ample headroom for the drive amplifier.

This ADC breaks the design difficulties of precision data acquisition signal chain

Figure 8. AD4000/AD4003 ADC Span Compression Mode of Operation

Overvoltage Clamp

In applications where the amplifier rails are greater than VREF and less than ground, the output can exceed the input voltage range of the device. When the positive input is out of range, current flows into REF through D1 (see Figure 9), disturbing the reference. Even worse, the reference could be pulled up to the absolute maximum reference level, potentially damaging the device.

When the analog input exceeds the reference voltage by ~400 mV, the AD4000/AD4003 ADC’s internal clamp circuit will turn on, and current will flow through the clamp into ground, preventing the input from rising further and potentially damaging the device.

This ADC breaks the design difficulties of precision data acquisition signal chain

Figure 9. AD4003 ADC Equivalent Analog Input Circuit

As shown in Figure 9, the internal overvoltage clamp of the AD4000/AD4003 ADC has a large external resistor (REXT = 200Ω), which eliminates the need for external protection diodes (and thus the need for additional board space) ). The clamp is turned on before D1 and has a maximum current sink capability of 50 mA. The clamp circuit prevents damage to the device by clamping the input voltage within a safe operating range while avoiding interference with the reference, which is especially important in systems where the reference is shared among multiple ADCs.

Efficient digital interface

The AD4000/AD4003 ADCs have a flexible digital serial interface with seven different modes and register programmability. Its Turbo mode allows the user to start outputting the results of the last conversion while the ADC is still converting, as shown in Figure 10. The combination of short transition times and turbo mode enables lower SPI clock rates, simplifies isolation solutions, reduces latency requirements for digital isolators, and increases processor options, including low-end processors/FPGAs or relatively low serial clock rates of low-power microcontrollers. For example, operating at 1 MSPS, the AD4003 ADC can use an SPI clock rate that is 2.5 times slower than the AD7982 ADC (25 MHz vs. 66 MHz). The user can write/read back register bits to enable the easy-to-use features of the AD4000/AD4003 ADC, and a 6-bit status word can be appended to the conversion result for diagnostics and register readback. The serial interface specification fully supports logic levels as low as 1.8 V, enabling full-speed throughput of 2 MSPS under these conditions. When Turbo mode is enabled, the minimum SCK rate required to operate the AD4003 ADC at 2 MSPS is 75 MHz.

This ADC breaks the design difficulties of precision data acquisition signal chain

Figure 10. AD4003 ADC Turbo Mode of Operation

AD4000/AD4003 ADC Performance

Operating at 1.8 V, the AD4000/AD4003 ADCs consume 14 mW/16 mW typical at 2 MSPS, have excellent linearity, ±1.0 LSB (±3.8 ppm) maximum, and guarantee 18 bits with no missing codes. Figure 11 shows the typical INL versus code performance of the AD4003 ADC. The AD4003 ADC can achieve better SINAD performance than the AD7982 ADC over an ultra-wide input frequency range up to Nyquist (Figure 12), allowing system designers to develop wider bandwidth and higher precision instrumentation. The AD4000/AD4003 ADCs are available in small 10-lead packages (available in 3 mm × 3 mm LFCSP and 3 mm × 5 mm MSOP options) and are pin-compatible with the AD798x/AD769x ADC family.

This ADC breaks the design difficulties of precision data acquisition signal chain

Figure 11. AD4003 ADC INL vs. Code

This ADC breaks the design difficulties of precision data acquisition signal chain

Figure 12. AD4003 ADC and AD7982 ADC SINAD vs. Input Frequency

The AD4000/AD4003 ADC shuts down automatically at the end of each conversion phase; therefore, its power consumption and throughput scale linearly, as shown in Figure 13. This feature makes the device ideal for low sampling rates (even down to a few Hz) and battery-operated portable and wearable systems. The first conversion result is always valid even in low duty cycle applications.

This ADC breaks the design difficulties of precision data acquisition signal chain

Figure 13. AD4003 ADC Power Consumption vs. Throughput

system applications

The AD4000/AD4003 ADC family combines ease of use, high performance, small size, and low power consumption, making it ideal for many precision control and measurement system applications, as shown in Figure 14. The AD4000/AD4003 ADC can reduce measurement uncertainty, improve repeatability, support high channel density, and improve throughput efficiency in automated test equipment, automated machine control equipment, and medical imaging equipment. This ADC is ideal for systems that require higher frequency performance to capture fast transient and time-of-flight information, such as power analyzers, mass spectrometers, and more.

This ADC breaks the design difficulties of precision data acquisition signal chain

Figure 14. AD4000/AD4003 ADC Termination System Application


With the AD4000/AD4003 ADC family, designers can solve the system-level technical challenges of precision data acquisition systems without major compromises and reduce overall system design time. The high performance of the AD4000/AD4003 ADCs improves measurement accuracy, while their small size and low system-level heat dissipation enable higher densities.

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