The article on the application of Tcl in Vivado starts from the basic grammar of Tcl and its application in Vivado. Following the last article xilinx” title=”xilinx”> “Customizing Vivado Design Implementation Process with Tcl” introduces how to extend or even customize FPGA design After the implementation of the process, a more detailed application scenario is brought out: how to use Tcl to partially edit the netlist or place and route on the completed layout design, so as to complete individual design changes in the shortest time and at the least cost need.
What is ECO
ECO refers to Engineering Change Order, that is, engineering change order. The purpose is to make small-scale modifications quickly and flexibly in the later stages of the design, so as to maintain the verified functions and timing as much as possible. The name ECO is inherited from the field of IC design, and its application in FPGA design is the first time, but this approach has actually been widely adopted in previous FPGA designs. Simply put, ECO is equivalent to the FPGA Editor on ISE.
But unlike FPGA Editor, ECO in Vivado is not an independent interface or some specific commands. To implement different ECO functions, different methods are needed.
ECO application scenarios and implementation process
The application scenarios of ECO mainly include: modify cell attributes, increase or decrease or move cells, and manual local wiring. There are also some complex scenarios that require multiple operations, such as putting RAM (or DSP) output registers in/out of RAMB (or DSP48), or connecting design internal signals to I/O for debugging probes etc.
For different application scenarios, the ECO implementation methods supported in Vivado are also slightly different. Some can be implemented with a graphical interface, while others can only use Tcl commands. However, the operations that can usually be implemented on the graphical interface can be implemented with one or more Tcl commands.
The implementation process of ECO is shown in the figure below:
The Design referred to in the first step is usually a design after complete layout and routing. If it is in engineering mode, you can directly open the implemented design in the IDE. If there is only a DCP file, whether it is generated in engineering mode or non-engineering mode DCP can be opened with the open_checkpoint command.
The second step is the meaning of ECO. We perform various operations on the layout and routing design, and then only perform partial layout/wiring on the changed part without the need to re-run the design as a whole, which saves a lot of time without destroying the existing The timing of convergence.
The third step is to generate bit files for download. At this time, you must directly input commands in Tcl Console or Tcl mode to generate bit files, instead of using the “Generate Bitstream” button on the IDE. The reason is that what the latter read is the original design that has been placed and routed before ECO, and the generated bit file is naturally unusable.
ECO realization process
Most of the attribute modification can be done through the IDE interface, as shown in the following figure:
For example, to modify the initial value of the register INIT or the truth table of the LUT, the user only needs to open the implemented design in the Vivado IDE, find and select the FF/LUT in the Device View, and then click on the left side of the FF/LUT. Select the attribute to be modified in the Cell Properties view on the side and modify it directly.
In addition to FF/LUT operations, we often need to modify the phase shift of the MMCM/PLL output clock. For this kind of application, the user does not need to regenerate the MMCM/PLL. Similar to the above method, it can be modified directly on the Device View after the layout.
Mobile/switching cells is the most basic scenario in the ECO operation of FF/LUT, and currently only this situation can be achieved graphically. If you want to delete cells, etc., you can only do it through Tcl commands.
The specific operation method is also quite simple. If you want to swap the positions of the cells, just select the two cells you need on the Device View, such as the two FFs shown in the figure above, then right-click to bring up the menu and select Swap Locations. If you want to move cells, it’s even easier. Just select FF in the picture and drag it to a new location.
When the user moves or changes the location of the cells, the nets connected to it will be highlighted in yellow, indicating that these nets need to be re-wired. What you need to do at this time is to select these nets in the figure, right-click to bring up the menu, and select Route for local wiring.
After partial wiring, remember to use the report_route_status command in the Tcl Console to check the wiring to ensure that there are no unrouted or partially routed nets. Add options to this command to report more detailed results, as shown in the figure below.
If you change to a slightly more complicated Tcl command with graphical Display, it will be more intuitive and at the same time it will be convenient to right-click to call out the command for targeted local wiring.
Manual wiring is an unconventional wiring method, which can only be performed on a graphical interface for one net at a time. The so-called manual wiring, in addition to completely manual selection of one node by one node, it also supports tools to automatically select resources for wiring. Usually we do not recommend a fully manual method. Vivado is a timing-driven tool, so the automatically selected routing results are already the best choice under the timing constraints.
In the Device View, select a net that has not been routed or previously unrouted (displayed as highlighted in red), right-click to call up the menu and select Enter Assign Routing Mode… to enter the manual routing mode.
Complex ECO scene
More than half of the space has been foreshadowing, in fact, the most practical ECO has not been mentioned yet. I believe that one of the features most users miss most in the FPGA Editor is probe. How to quickly connect an internal signal to the FPGA pin without re-layout and routing, directly update the bit file and download and debug it. I have been asked several times by customers, and many people also deeply regret that this approach is not supported in Vivado.
In fact, such similar functions have always been supported in Vivado. The only problem is that there is no graphical interface for one-click operation (relevant development work is already in progress). But benefiting from the flexibility of Tcl, we can implement the probe function in a more targeted manner with higher efficiency.
Tcl operation commands
In UG835, the Tcl commands supported by Vivado are classified according to Category. The commands listed in the Netlist directory are those needed to implement ECO.
The ECO that usually involves adding or subtracting cells is basically implemented in three steps: first create related cells and/or nets with create_cell / create_net, etc., and then use commands such as disconnect_net / connect_net to correct the connection relationship that is affected by the changes to cells and nets. Finally, use route_design plus option to complete local wiring.
Different Vivado versions have slightly different restrictions on this type of ECO modification. For example, in versions after 2014.1, you need to use unplace_cell to release the cell from the current layout position before changing the connection relationship of the cell to complete the new connection relationship. After that, use place_cell to put it on the new layout position.
In terms of specific operations, you can modify specific Tcl commands based on Vivado’s prompts or error messages, but the operating ideas are almost the same as the available commands.
This is a Tcl script that implements the probe function on Vivaod. It has been written as a proc subroutine, which is simple and easy to understand. It can be called directly or made into Vivado’s embedded extended commands. To call it to generate probe, you only need to source the script first, and then enter the command in the Tcl Console as shown below.
Vivado% addProbe inst_1/tmp_q D9 LVCMOS18 my_probe_1
This script has been tested on Vivado 2014.3 and 2014.4. Only one probe can be added at a time, and the signal name, pin location, level standard and probe name must be entered in the above order. Because it does not have the pre-check function, you may encounter some error messages and make it impossible to continue. For example, when the selected signal is INTRASITE that only exists in SLICE, it cannot be pulled out to the pin. Another example is the misspelling of the level standard when entering the command, which will also cause the problem that Tcl has partially modified the Vivado database and cannot continue. At this time, you can only close the opened DCP and choose not to save and start over.
Users can extend this Tcl script according to their own needs, or imitate the writing of this Tcl to achieve other ECO requirements. For example, at the beginning of the article, I mentioned a scenario where the RAMB output level FF is pulled out to Fabric. The basic implementation method and idea are similar: first change the attribute of the RAMB output port REG to 0, and then create a For the new FF, connect its input to the RAMB output, and then connect the FF output to the cell driven by the original RAMB output, and complete the correct connection between the FF clock and the reset terminal, and then choose a suitable location to place the new FF, and finally Local wiring for newly added nets.
It can be seen that although the ECO realized with Tcl is not as simple and intuitive as the graphical interface, it brings maximum freedom to the user. It is entirely up to the user to decide how to modify the design, even after the final placement and routing sequence closure has been completed, it can directly change the connection relationship of those underlying units, or even increase or decrease the design.
ECO’s development on Vivado
After more than two years of development, there have been many ways to implement ECO on Vivado. In addition to the graphical techniques mentioned above, there are also user-defined Tcl commands and scripts. With the introduction of the Xilinx Tcl Store, users can download and use Tcl scripts just like downloading and using apps in the App Store. This simplifies the application of Tcl on Vivado and further expands the in-depth and refined use of Tcl, including Tcl in Application on ECO.
Many useful scripts have been added to Vivado 2014.4. After installing Vivado, just open the Tcl Store, find Debug Utilities, click Install, wait a while, you can see a Tcl proc of add_probe is installed in your Vivado.
This add_probe is based on the above addProbe example. It can not only add probes, but also change the signals connected to existing probes. In addition, this script uses the argument writing method. Click the program to see the help, so it is not necessary to input the signal, level standard and other options in order, and there is no problem with inputting errors. In addition, the pre-check and error correction functions are added. If there is a problem, it will report an error and exit without changing the Vivado database, which is more efficient.
In addition, there are many other useful scripts on the Tcl Store. You are welcome to try them out and give us valuable feedback. Although there are very few ECO scripts in it, we have been adding them all the time. In addition, Tcl Store is a completely open source environment based on GitHub. Of course, you are welcome to upload useful Tcl scripts in your hands to supplement it.
In general, ECO is a relatively big proposition, because too many changes are required, and it is actually difficult to limit it to a GUI interface. The purpose of this article is to give everyone a basic understanding of the implementation of ECO on FPGA, to sort out the seemingly complex and disorderly process, the so-called “seeing a leaf and knowing the autumn, and a glimpse of the whole leopard”, hoping to bring more User confidence, it is not difficult to use Vivado well.