“As the resolution of the SAR ADC increases, the number of components in the CDAC unit increases linearly, but the matching requirements of these components cause the square-law area to increase. To limit the total number of components, bridging or scaling components are often used to split the DAC into smaller sub-DACs. These scaling elements are not unit specs, and their parasitic effects can cause further mismatches and errors. Usually due to area constraints, matching more than 10~11 bits is not feasible for microcontroller integration. Therefore, some form of calibration must be performed on the ADC DAC components to meet the higher resolution and accuracy requirements.This article will introduce a differential, area-effective 16-bit

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For applications that previously used discrete ADCs, including energy metering, handheld medical devices, industrial control systems, power management systems, gaming consoles, and instrumentation, it is increasingly possible to provide high-performance analog functionality with low-cost microcontrollers. In general-purpose control system applications, Nyquist ADCs are often required to have both low latency, high bandwidth and low power consumption. At the same time, their accuracy reaches about 14 effective digits (14-bit ENOB), and the price is also popular. accepted. With so many demands, most of today’s SAR and Sigma-Delta (DS) ADCs will be obsolete because it is too difficult to meet frequency and latency requirements while meeting low-cost and low-power goals. This article will introduce a low-power 16-bit SAR ADC based on a self-calibrating, self-checking architecture, which is equipped with a dual-bridge split CDAC and a high-speed three-level comparator. Production data shows that this architecture is accurate up to 14.5 ENOB, and the total cost (implementation and test) is significantly lower than most of the best-selling 12-bit SAR ADCs on the market.

As the resolution of the SAR ADC increases, the number of components in the CDAC unit increases linearly, but the matching requirements of these components cause the square-law area to increase. To limit the total number of components, bridging or scaling components are often used to split the DAC into smaller sub-DACs. These scaling elements are not unit specs, and their parasitic effects can cause further mismatches and errors. Usually due to area constraints, matching more than 10~11 bits is not feasible for microcontroller integration. Therefore, some form of calibration must be performed on the ADC DAC components to meet the higher resolution and accuracy requirements. This article will describe the design of a differential, area-efficient 16-bit self-calibrating SAR ADC.

Figure 1: Fully differential ADC architecture with 2 complementary CDACs.

**ADC Architecture**

Figure 1 shows the ADC architecture without the channel multiplexer. SAR ADCs typically consist of DACs and comparators in a feedback loop with logic including successive approximation registers. A DAC usually consists of a set of binary weighted elements, in this case capacitors. Some applications often require the ability to convert differential input signals of unknown polarity. Converting differential signals also helps improve the accuracy of the results through common-mode noise rejection.

Implementing a differential ADC often faces a number of constraints, one of which is the need to keep the comparator’s input within its common-mode range during successive approximation. When the comparator is auto-zeroed at a common-mode voltage, if the input deviates from this common-mode voltage, the conversion result will be erroneous, thereby increasing non-linearity. To prevent this, we added a smaller, lower power “non-critical” comparator. This comparator is paired with a negative-side DAC (responsible for sampling VIN-) for partial successive approximation. This keeps the comparator negative input V- close enough to VCM to ensure that the comparator is accurate to within 1LSB. The number of approximations required on the negative side is determined by the common-mode rejection ratio (CMRR) of the comparator and the resolution of the ADC. The higher the CMRR, the fewer approximations are required. For example, if the CMRR of the comparator in a 12-bit ADC is 66dB, only 2 approximations are required on the negative side (1/2 of the 12-bit LSB = 78dB, so the negative-side approximation reduces the |VCMV-| voltage by 12dB) .

We implemented a 16-bit ADC (1/2LSB = 102dB) and the CMRR of the comparator is about 72dB, so 5 approximations are required (25 = 30dB). For a 5-bit SAR, the minimum input voltage that the “non-critical” comparator must resolve is VREFH/32. After completing the partial successive approximation on the negative side, a full 16th-order approximation is performed using a precision comparator and a positive side DAC (responsible for sampling VIN+). The two comparator outputs are captured by the SAR logic to control the corresponding DACs for successive approximation. Subtracting the positive-side result and the negative-side result will result in an uncalibrated result, and the final conversion result can be obtained by subtracting the preset calibration value from the result. This differential mode operates up to 320kS/s. In single-ended mode, partial successive approximation is not required on the negative side, so the maximum operating speed can reach 460kS/s. In addition, the ADC features a low-resolution 12-bit mode that operates up to 1MS/s.

**CDAC array**

CDAC is the most important component in SAR. The linearity of a SAR ADC depends on the capacitor matching in the capacitor array. Split capacitor structures are a common method of limiting chip area. The CDAC topology shown in Figure 2, combined with calibration, provides a design that achieves the best trade-off between capacitor array size (96 capacitors), speed, noise, and linearity. Each capacitor represents a set of unit capacitances. By calibrating the most significant bit capacitance, the size of the unit capacitance can be reduced. This design uses a unity fringe capacitor of about 125fF, which provides adequate matching to the uncalibrated capacitor and keeps the 16-bit kT/C noise below 1LSB. The CDAC is divided into 3 binary weighted sub-DACs based on unit size capacitance. The most significant bit (MSB) sub-DAC contains 5 bits, the intermediate significant bit (ISB) sub-DAC contains 5 bits, and the least significant bit (LSB) sub-DAC contains 6 bits. The LSB section is built into a 5-bit array with half-size capacitors for bit 0 and termination.

Figure 2: Fully differential 5b-5b-6b split CDAC topology with 2 bridge capacitors.

**ADC calibration**

There are a number of calibration methods for SAR ADCs, some using digital correlation-based calibration, others using correlation techniques to measure the difference in capacitance ratios in the DAC and then either modify the DAC components by analog trimming or adjust the result digitally. The measurement method used by the ADC in this article is to determine the capacitance error value by measuring the capacitance ratio difference, and then modify the result by digital adjustment. The MSB capacitors of both the positive and negative CDACs are calibrated. In order not to produce large nonlinearities after adjusting the SAR results, the CDAC before calibration must be monotonic, and resizing the scaling capacitor Csc1 (Figure 3) to be slightly larger than the ideal value can guarantee monotonicity. Figure 3 illustrates this concept.

To determine the calibration error value, each MSB capacitance (controlled by bits 15:11) is compared to the combination of all least significant bit capacitances. For example, one step of the calibration is to compare the bit 11 capacitance (1C) with the bit 10:0 capacitance and the last bit capacitance (slightly larger than 1C due to Csc1 being too large). The next step is to compare the bit 12 cap (2C) with the bit 11:0 cap and termination cap (slightly larger than 2C). And so on, each MSB capacitor does this. Calibration coefficients are accumulated and stored in memory, requiring less than 128 bits of storage per ADC. After a normal ADC conversion is complete, the calibration result is obtained by subtracting the calibration value corresponding to the MSB result from the uncalibrated result.

Then, applying a gain factor based on the accumulated calibration coefficients can generate the final conversion result. This calibration method compensates for the mismatch between the MSB capacitors as well as the mismatch and parasitic effects of the first scaling capacitor. It must be pointed out that in order to improve the linearity of the uncalibrated capacitors and to tolerate process gradients and limit the calibration range, a common centroid layout technique must be used. In addition, a dummy capacitor ring is used at the edge of the capacitor array to ensure that all unit capacitors in the capacitor array have the same peripheral structure.

Figure 3: Nonlinearity and ways to improve CDAC linearity.

Table 1: Typical and worst-case Monte Carlo simulation results for CDAC INL and DNL.

Figure 4: Fully differential comparator with capacitive coupling and auto-zero.

In comparator design, the main trade-off is speed versus accuracy. Accuracy is guaranteed by providing adequately high gain, low offset, and low input-referred noise. Comparator offset causes a shift in ADC transfer characteristics, but does not affect ADC linearity. In our implementation, the offset is eliminated by auto-zeroing techniques. The comparator needs enough gain to account for voltages less than 1LSB (as low as around 15mV in 16-bit mode) and provide a response within the specified delay time. In 16-bit mode, the maximum ADC clock is 12MHz, in which case the comparator needs to complete each comparison in about half a cycle (ie 41.6ns).

A three-stage comparator is chosen here to obtain a compromise between speed and gain. Each stage is self-zeroed independently and capacitively coupled to the next stage. Note that the first two stages are fully differential comparators and the third stage is a single-ended comparator. Figure 5 shows a simplified schematic of the comparator stages. Utilizing a folded cascode structure provides sufficient gain to address the voltage levels associated with a 16-bit ADC. During the ADC sampling/auto-zero stage, the gates of the differential pair M1-M2 are connected to analog ground (cazd is high) and the output stage is configured for low gain via M13 – M14 (casz is high) in order to store Offset on C3 and C4.

Figure 5: Minimum/maximum INL in LSB versus reference voltage, temperature, and sampling frequency (at maximum slew rate in 16-bit differential mode).

At the end of the autozero phase, the first casz is deasserted and then cazd is deasserted using non-overlapping clock phases. The ADC then starts the successive approximation stage, the comparator stage switches to a high gain configuration, and the input signal is amplified by the folded cascode gain stage. During the successive approximation cycle, the comparator output stage is reset by M12 and the DAC can stabilize (clk is high). Next, clk is de-asserted and a compare operation is performed. Comparator placement is critical to the ADC’s performance, taking special care to prevent coupling of analog and digital signals.

**Experimental results**

The ADC is fabricated on a 90nm CMOS process, and the ADC circuit has been integrated into the 90nm microcontroller family and is currently in production. Four devices were randomly selected in a wafer production batch, and the measured ADC integral nonlinearity (INL) errors are shown in Figure 5. The test conditions for the minimum and maximum INL shown in the figure are as follows: maximum slew rate, clock frequency from 1MHz to 12MHz (maximum clock frequency), voltage from 1.71V to 3.6V, temperature from -40°C to 125°C.

Figure 6 shows the ENOB at 8MHz and 12MHz clock rates, reaching nearly 15 bits of ENOB at 11kS/s slew rate.

Figure 6: Relationship between SAR ADC ENOB and sampling frequency under typical conditions.

Figure 7 is a photo of the ADC on the microcontroller chip. The CDACs are located in the center section, while the switches are located under each fringe capacitor cell. The comparator and current reference are below the CDAC, and the channel multiplexer is above the CDAC, at the top of the circuit.

Figure 7: Microcontroller chip photo (ADC highlighted).

**in conclusion**

With 90nm CMOS technology, a low-power differential self-calibrating 460kS/s 16-bit rail-to-rail input SAR A/D converter has been successfully implemented using metal fringe capacitors. This ADC has a measured current consumption of 800mA at full speed and is suitable for a variety of applications. Silicon measurements show an overall performance of 13.5-14.5 ENOB. The circuit is now integrated into the 90nm microcontroller family and is currently in production.

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